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general description the max5096/MAX5097 easy-to-use, dual mode, dc-dc converters operate as ldo (low dropout) or switch-mode buck converters. at a high output load, the converters operate as high-efficiency pulse-width- modulated (pwm) switch-mode converters and reduce the power dissipation. the devices switch to a low-qui- escent-current (i q ) ldo mode of operation at light load. during the key-off condition, the system? microcon- troller drives the ldo/ buck input on the fly and forces the max5096/MAX5097 into ldo mode, thereby reduc- ing the quiescent current significantly. in buck mode, the max5096/MAX5097 operate from a 5v to 40v input voltage range and deliver up to 600ma of load current with excellent load and line regulation. the fixed-switching frequency versions of 135khz and 330khz are available. the max5096/MAX5097 dc-dc internal oscillator can be synchronized to an external clock. external compensation and a current-mode control scheme make it easy to design with. in ldo mode, the max5096/MAX5097 operate from a 4v to 40v input voltage. the ldo mode operation is intended for a lower output load current of up to 100ma. the quiescent current at 100? load in ldo mode is only 41? (typ). the max5096/MAX5097 feature an enable input that shuts down the device, reducing the current consump- tion to 6? (typ). additional features include a power-on reset output with a capacitor-adjustable timeout period, programmable soft-start, output tracking, output over- load, short-circuit and thermal shutdown protections. the max5096/MAX5097 operate over the -40? to +125? automotive temperature range and are avail- able in thermally enhanced 20-pin tssop or 16-pin tqfn packages. applications automotive industrial features ? high-efficiency switcher mode (buck mode) or low-quiescent-current linear regulator (ldo mode) operation ? wide operating input voltage range +5v to +40v buck mode +4v to +40v ldo mode ? fixed 3.3v or 5v and adjustable (1.24v to 11v) output voltage versions ? 6? (typ) shutdown current ? fixed 135khz or 330khz switching frequency ? external frequency synchronization ? programmable soft-start ? integrated microprocessor reset ( reset ) circuit with programmable timeout period ? thermal and short-circuit protection ? -40? to +125? automotive temperature range ? thermally-enhanced package dissipates 2.6w at t a = +70? (16-pin tqfn) 1.7w at t a = +70? (20-pin tssop) max5096/MAX5097 40v, 600ma buck converters with low- quiescent-current linear regulator mode ________________________________________________________________ maxim integrated products 1 19-0603; rev 0; 7/06 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. ordering information part temp range pin-package pkg code max5096 aate+* -40? to +125? 16 tqfn-ep** t1655-2 max5096bate+ -40? to +125? 16 tqfn-ep** t1655-2 max5096aaup+* -40? to +125? 20 tssop-ep** u20e-4 max5096baup+* -40? to +125? 20 tssop-ep** u20e-4 MAX5097 aate+ -40? to +125? 16 tqfn-ep** t1655-2 MAX5097bate+* -40? to +125? 16 tqfn-ep** t1655-2 MAX5097aaup+* -40? to +125? 20 tssop-ep** u20e-4 MAX5097baup+* -40? to +125? 20 tssop-ep** u20e-4 tqfn + lx 16 1 2 3 4 12 11 10 9 15 14 13 5678 in in lx en out adj ldo/buck sgnd reset bp sync ss ct comp pgnd max5096 MAX5097 top view 20 19 18 17 16 15 14 1 2 3 4 5 6 7 lx lx n.c. en pgnd in in in top view max5096 MAX5097 out adj n.c. bp 13 8 n.c. 12 9 comp sync 11 10 ct ss sgnd tssop ldo/buck reset + pin configurations * future product?ontact factory for availability. + denotes lead-free package. ** ep = exposed pad. dual mode is a trademark of maxim integrated products, inc.
max5096/MAX5097 40v, 600ma buck converters with low- quiescent-current linear regulator mode 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. (all voltages referenced to pgnd, unless otherwise noted.) in (transient, 1ms) ..................................................-0.3v to +45v sgnd ....................................................................-0.3v to +0.3v lx....................................................................-1v to (v in + 0.3v) lx current ................................................................................2a en ................................................................-0.3v to (v in + 0.3v) bp, sync, ldo/ buck , reset to sgnd...............-0.3v to +12v bp, reset output current..................................................25ma ct, ss, adj, comp to sgnd ....................-0.3v to (v bp + 0.3v) out ........................................................................-0.3v to +11v out short-circuit duration ........................................continuous continuous power dissipation (t a = +70?)* 16-pin tqfn (derate 33.3mw/? above +70?) ........2666mw 20-pin tssop (derate 21.7mw/? above +70?) ......1739mw thermal resistance: ( ja , 16-pin tqfn)* ...................................................30.0?/w ( jc , 16-pin tqfn).......................................................1.7?/w ( ja , 20-pin tssop)* .................................................46.0?/w ( jc , 20-pin tssop)........................................................2?/w operating temperature range .........................-40? to +125? junction temperature ......................................................+150? storage temperature range .............................-60? to +150? lead temperature (soldering, 10s) .................................+300? electrical characteristics (v in = +14v, i out = 1ma, c in = 100?, c out = 22?, l = 22?, c bp = 1?, v en = +2.4v (figure 2), sgnd = pgnd = 0v, t a = t j = -40? to +125?, unless otherwise noted. typical values are at t a = t j = +25?.) (note 1) parameter symbol conditions min typ max units system input input voltage range (ldo mode) v in_ldo ldo/ buck = high 4 40 v input voltage range (buck mode) v in_buck ldo/ buck = low 5 40 v internal input undervoltage lockout v uvlo v bp rising 3.5 3.65 3.9 v internal input undervoltage lockout hysteresis v uvlo_hys v bp falling 0.185 v bp (internal regulator) output voltage v bp v in = +4.5v, i bp = 100? 3.75 4 4.20 v i q ldo/ buck = high, measured at input supply return, v out = 5v, i out = 100? t a = -40? to +125? 41 70 quiescent supply current ( ldo mode) i q ldo/ buck = high, measured at input supply return, v out = 5v, i out = 100ma t a = -40? to +125? 44 100 ? buck converter no-load supply current i q_buck v in = 14v, v out = 5v, i out = 0 680 ? t a = -40? to +125? 619 shutdown supply current i shdn v en = 0v, measured from en t a = -40? to +85? 612 ? *as per jedec 51 standard?ultilayer board.
max5096/MAX5097 40v, 600ma buck converters with low- quiescent-current linear regulator mode _______________________________________________________________________________________ 3 electrical characteristics (continued) (v in = +14v, i out = 1ma, c in = 100?, c out = 22?, l = 22?, c bp = 1?, v en = +2.4v (figure 2), sgnd = pgnd = 0v, t a = t j = -40? to +125?, unless otherwise noted. typical values are at t a = t j = +25?.) (note 1) parameter symbol conditions min typ max units buck mode supply current (buck converter on) i s ldo/ buck = low, v adj = 1.4v, max5096, no switching 135khz version 693 980 ? supply current (buck converter on) i s ldo/ buck = low, v adj = 1.4v, MAX5097, no switching 330khz version 720 1000 ? 5v version, 5.5v v in 40v, no load 4.85 5 5.12 fixed output voltage v out 3.3v version, 5.5v v in 40v, no load 3.196 3.3 3.391 v adj set point v fb 50% duty cycle, no load 1.189 1.237 1.280 v adj input bias current i fb v adj = 1.5v 5 100 na v adjth_r adj rising 125 dual mode adj threshold v adjth_f adj falling 62 mv maximum duty cycle d max v adj = 0.5v 100 % error amplifier transconductance gm ea v comp = v adj , i comp = ?0? 55 136 210 ? adjustable output voltage range v adj 1.237 11.000 v minimum output current i out v in = 6.5v to 40v 600 ma switch current limit i sw_lim v in = 6v to 40v 1.15 1.5 1.90 a internal switch on-resistance r ds ( on ) v in = 14v, i drain = 100ma 0.9 2.1 ? switch leakage current i sw_l v in = 40v, v adj = 1.5v 0.05 3a v in = 14v, v out = 5v, i out = 400ma 85 efficiency v in = 14v, v out = 3.3v, i out = 400ma 81 % max5096 120 135 148 khz switching frequency f sw MAX5097 300 330 350 khz max5096 120 500 khz synchronization sync input f sync MAX5097 300 500 khz sync input high threshold v synch v bp = 4v 2.0 v sync input low threshold v syncl v bp = 4v 0.8 v sync input minimum high pulse width 250 ns sync input leakage v sync =11v 1 a ldo mode guaranteed output current i out (note 2) 100 ma
max5096/MAX5097 40v, 600ma buck converters with low- quiescent-current linear regulator mode 4 _______________________________________________________________________________________ electrical characteristics (continued) (v in = +14v, i out = 1ma, c in = 100?, c out = 22?, l = 22?, c bp = 1?, v en = +2.4v (figure 2), sgnd = pgnd = 0v, t a = t j = -40? to +125?, unless otherwise noted. typical values are at t a = t j = +25?.) (note 1) parameter symbol conditions min typ max units 5v version, max5096b/MAX5097b, 5.5v v in 40v, i out = 10ma 4.89 5 5.09 v output voltage v out 3.3v version, max5096a/MAX5097a, 4v v in 40v, i out = 10ma 3.219 3.3 3.378 v adj set point v adj i out = 10ma 1.21 1.2375 1.26 v adj input bias current i fb v adj = 4v 0.5 100 na adjustable output voltage range v adj i out = 10ma 1.237 11.000 v dropout voltage ? v do i out = 100ma, v out = 0.98 x v out(nominal) (5v version only), max5096b/MAX5097b 0.37 v startup response time rising edge of en to v out = 10% v out(nominal) , r l = 500 ? , v adj = sgnd, ldo/ buck = 4v, c ss = 2nf 300 ? 5v version, +5.5v v in +40v, i out = 100ma 0.125 line regulation ? v out / ? v in 3.3v version, +4v v in +40v, i out = 100ma 0.093 mv/v t j = +25? 0.242 0.374 5v version, i out = 100? to 100ma, v in = +14v t j = -40? to +125? 0.242 1 t j = +25? 0.164 0.237 load regulation ? v out / ? i out 3.3v version, i out = 100? to 100ma, v in = +14v t j = -40? to +125? 0.164 1 mv/ma power-supply rejection ratio psrr i out = 10ma, f = 100hz, 500mv p-p , v out = +5v, v in = +14v 60 db short-circuit current i sc v in = 6v 150 330 500 ma buck mode (ldo mode transition) ldo/ buck high threshold 2.0 v ldo/ buck low threshold 0.8 v ldo/ buck input leakage ldo/ buck = 11v 1 a transition timing from ldo mode to buck mode falling edge of ldo/ buck to buck converter on 32 clock periods transition timing from buck mode to ldo mode rising edge of ldo/ buck to ldo operation 100 ? soft-start, enable (en) and reset soft-start charge current i ss v ss = 0.1v 3 5 7 a soft-start reference voltage v ss-ref v out = v out(nominal) - 20% 0.9 0.99 1.1 v en high-voltage threshold v enh en = high, regulator on 1.4 v
max5096/MAX5097 40v, 600ma buck converters with low- quiescent-current linear regulator mode _______________________________________________________________________________________ 5 electrical characteristics (continued) (v in = +14v, i out = 1ma, c in = 100?, c out = 22?, l = 22?, c bp = 1?, v en = +2.4v (figure 2), sgnd = pgnd = 0v, t a = t j = -40? to +125?, unless otherwise noted. typical values are at t a = t j = +25?.) (note 1) parameter symbol conditions min typ max units en low-voltage threshold v enl regulator off 0.4 v en input pulldown v en = 2v, ldo/ buck = 4v 0.5 ? reset voltage threshold high v reset_h v out rising 90 92 94 % v out reset voltage threshold low v reset_l v out falling 87 90 92 % v out reset output-low voltage v rl i sink = 1ma 0.2 v reset output-high leakage current i rh v reset = 5v, v adj = 1.5v 1 a reset output minimum timeout period c ct = 0 25 s v out to reset delay v out falling 10mv/?, c ct = 0 6 ? delay comparator threshold v ct_th v ct rising 1.18 1.2374 1.29 v delay comparator threshold hysteresis 100 mv ct charge current i ch 0.74 1 1.20 ? ct discharge current i disch v ct = 1v 13.8 ma thermal shutdown thermal shutdown temperature t j ( shdn ) temperature rising +165 ? thermal shutdown hysteresis ? t j ( shdn ) 20 c note 1: limits to -40? are guaranteed by design. note 2: the continuous maximum output current from ldo is limited by package power dissipation.
max5096/MAX5097 40v, 600ma buck converters with low- quiescent-current linear regulator mode 6 _______________________________________________________________________________________ t ypical operating characteristics (v in = +14v, v en = +2.4v, MAX5097aate+, figures 2 and 4, t a = +25?, unless otherwise specified.) output voltage vs. input voltage (ldo mode) max5096 toc01 input voltage (v) output voltage (v) 10 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 1 100 i out = 50ma output voltage vs. input voltage (buck mode) max5096 toc02 input voltage (v) output voltage (v) 10 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 1100 i out = 600ma 0 10 70 30 20 40 50 60 80 -40 -10 5 20 -25 35 50 95 80 110 65 125 quiescent supply current vs. temperature (ldo mode) max5096 toc03 temperature ( c) quiescent supply current ( a) v in = 14v v out = 3.3v i out = 100ma i out = 100 a i out = 0 640 660 650 680 670 700 690 710 no-load supply current vs. temperature (buck mode) max5096 toc04 v in = 14v v out = 3.3v -40 -10 5 20 -25 35 50 95 80 110 65 125 temperature ( c) no-load supply current ( a) 0 4 2 8 6 12 10 14 shutdown current vs. temperature max5096 toc05 -40 -10 5 20 -25 35 50 95 80 110 65 125 temperature ( c) shutdown current ( a) v en = 0v v in = 14v 3.0 3.1 3.2 3.3 3.4 3.5 output voltage vs. temperature (ldo mode) max5096 toc06 output voltage (v) -40 -10 5 20 -25 35 50 95 80 110 65 125 temperature ( c) v out = 3.3v i out = 10ma i out = 100 a i out = 10ma 3.24 3.28 3.26 3.32 3.30 3.36 3.34 3.38 output voltage vs. temperature (buck mode) max5096 toc07 -40 -10 5 20 -25 35 50 95 80 110 65 125 temperature ( c) output voltage (v) v out = 3.3v i out = 100 a i out = 100ma i out = 600ma 0 0.04 0.02 0.10 0.08 0.06 0.16 0.14 0.12 0.18 040 20 60 80 100 dropout voltage vs. output current (ldo mode) max5096 toc08 output current (ma) dropout voltage (v) v out = 5v 0 30 20 10 40 50 60 70 80 90 100 0.01 0.1 1 efficiency vs. load current (v out = 3.3v) max5096 toc09 load current (a) efficiency (%) v in = 5v v in = 14v v in = 24v v in = 40v f sw = 330khz
max5096/MAX5097 40v, 600ma buck converters with low- quiescent-current linear regulator mode _______________________________________________________________________________________ 7 t ypical operating characteristics (continued) (v in = +14v, v en = +2.4v, MAX5097aate+, figures 2 and 4, t a = +25?, unless otherwise specified.) 0 30 20 10 40 50 60 70 80 90 100 0.01 0.1 1 efficiency vs. load current (v out = 5v) max5096 toc10 load current (a) efficiency (%) v in = 40v v in = 5.5v v in = 24v v in = 14v 2ms/div load-transient response (ldo mode) i out 50ma/div v out 50mv/div max5096 toc11 v in = 14v i out = 100 a to 50ma 1ms/div load-transient response (buck mode) i out 200ma/div v out ac-coupled 100mv/div max5096 toc12 v in = 14v i step = 300ma to 600ma 10ms/div v in startup response (ldo mode) v in 10v/div reset 5v/div max5096 toc13 v in = 14v i out = 0a c ct = 0.047 f v en 10v/div v out 2v/div 10ms/div enable startup response (ldo mode) v in 10v/div reset 5v/div max5096 toc14 v in = 14v i out = 100ma c ct = 0.047 f v en 5v/div v out 2v/div 10ms/div v in startup response (buck mode) v in 10v/div reset 5v/div max5096 toc15 v in = 14v i out = 0a c ct = 0.047 f v en 5v/div v out 2v/div 10ms/div enable startup response (buck mode) v in 10v/div reset 5v/div max5096 toc16 v in = 14v i out = 600ma c ct = 0.047 f v en 5v/div v out 2v/div 100ms/div shutdown response through v in (ldo mode) v in 10v/div reset 5v/div max5096 toc17 i out = 50ma v en 10v/div v out 2v/div 100ms/div shutdown response through v in (buck mode) v in 10v/div reset 5v/div max5096 toc18 i out = 50ma v en 10v/div v out 2v/div
max5096/MAX5097 40v, 600ma buck converters with low- quiescent-current linear regulator mode 8 _______________________________________________________________________________________ t ypical operating characteristics (continued) (v in = +14v, v en = +2.4v, MAX5097aate+, figures 2 and 4, t a = +25?, unless otherwise specified.) 2 s/div lx voltage and inductor current max5096 toc19 i out = 0a v lx 5v/div inductor current 200ma/div 1 s/div lx voltage and inductor current max5096 toc20 i out = 600ma v lx 10v/div inductor current 500ma/div 1 s/div lx voltage, sync input, and inductor current max5096 toc21 v lx 10v/div inductor current 500ma/div sync input 5v/div 400 s/div transition from buck mode to ldo mode max5096 toc22 ldo/buck 5v/div i out 100ma/div v out ac-coupled 200mv/div v in = 14v i out = 100ma 100 s/div transition from ldo mode to buck mode max5096 toc23 ldo/buck 3v/div i out 100ma/div v out ac-coupled 200mv/div v in = 14v i out = 100ma
max5096/MAX5097 40v, 600ma buck converters with low- quiescent-current linear regulator mode _______________________________________________________________________________________ 9 pin description pin tqfn tssop name function 14 pgnd power ground. return path for p-channel power mosfet driver. connect the input capacitor return, freewheeling diode anode, and output capacitor return terminals to pgnd. 25 sgnd signal ground. connect sgnd to pgnd near the input bypass capacitor return terminal. 36 reset open-drain, active-low reset output. reset asserts low when out drops below the reset threshold. when output rises above 92% of the programmed level, reset becomes high impedance after the reset timeout period. connect a pullup resistor from reset to the converter output to create a logic output. 47bp 4v internal regulator output. bypass bp to sgnd with a 1? or greater ceramic capacitor. 59 sync synchronization input. connect sync to an external clock for synchronization. connect sync to sgnd when not used. 610ss soft-start timer input. connect an external capacitor from ss to sgnd to adjust the soft- start timeout period (see the soft-start (ss) section). 711ct reset timeout period. connect a capacitor from ct to sgnd to set the reset timeout period (see the power-on reset output reset section). 81 2 comp buck converter (buck mode) control loop compensation. see the compensation network section for compensation network design. ldo mode does not need external compensation. 913 ldo/ buck ldo mode/buck mode select. drive ldo/ buck low to select the buck mode. the buck mode activates after 32 internal/external clock cycles. force the ldo/ buck high (> 2v), to select ldo mode. the buck mode stops and ldo mode is activated with a 100? delay. 10 15 adj regulator output feedback point. connect adj to sgnd for a fixed 3.3v (max5096a/MAX5097a) or 5v (max5096b/MAX5097b). for adjustable output voltage, use an external resistive divider to set v out . v adj regulating set point is 1.237v. 11 16 out converter output. out must always be connected to the regulator output. connect at least a 22? low-esr (equivalent series resistance) capacitor from out to pgnd for stable operation. 12 17 en enable input. en is internally pulled to ground. drive en high to turn on the regulator. force en low or leave unconnected to place the device in shutdown mode. 13, 14 19, 20 lx drain connection of internal p-channel high-side switch 15, 16 1, 2, 3 in regulator input. bypass in to pgnd with a parallel combination of low-esr ceramic and aluminum capacitor to handle the input ripple current. ? , 14, 18 n. c. no connection. not internally connected. ep ep ep exposed pad. connect externally to a large ground plane (sgnd) for improved heat dissipation. do not use ep as an electrical ground connection.
max5096/MAX5097 40v, 600ma buck converters with low- quiescent-current linear regulator mode 10 ______________________________________________________________________________________ + - - + - - + + - - + gm v ref 0.9 ? current limiter reset internal 4v ldo bp in adj lx reset gate driver mux en pgnd ldo/buck l v out c in pwm c out sync ct ss 0.12v feedback selector buck mode gm amplifier fb ldo/ buck selector pwm comparator dc-dc enable oscillator and ramp generator mode selector ss out ldo mode amplifier ss dc current sense comp r c c c v out sgnd v in fb syncro c bp r 2 r pu r 1 c ss c ct bias soft- start internal bandgap uvlo thermal protection v ref max5096 MAX5097 c p figure 1. simplified diagram
detailed description the max5096/MAX5097 are easy-to-use, high-efficien- cy, pwm current-mode, step-down switching convert- ers in normal operation. the max5096/MAX5097 have an internal high-side p-channel 0.9 ? switch and use a low forward-drop freewheeling diode for rectification. in buck mode, the p-channel switches at the 135khz or 330khz frequency. buck mode uses a current-mode control architecture that offers excellent line-transient response, easier frequency compensation, and cycle- by-cycle current limiting. the buck converter is com- pensated externally for a selected value/type of output inductor and capacitor. the internal p-channel switch acts as a pass element when operating in the low-quiescent-current ldo mode. the ldo mode can be selected on the fly through the ldo/ buck input. during the key-off condition, the sys- tem? microcontroller drives the ldo/ buck input high and forces the max5096/MAX5097 into ldo mode, reducing the quiescent current to 1? (typ). when in ldo mode, the device is capable of delivering up to 100ma, which may be limited by the device power dis- sipation. the ldo and switcher share the same pass element and the reference; however, the error ampli- fiers are different with their own compensation schemes. the max5096/MAX5097 include an integrated micro- processor reset circuit with an adjustable reset timeout period. the internal reset circuit monitors the regulator output voltage and asserts reset low when the regula- tor output falls below the reset threshold voltage. other features include an enable input, externally program- mable soft-start, optimized current-limit protection in both ldo and buck modes, and thermal shutdown. enable input (en) en is a logic-level enable input that turns the device on or off. the logic-high and logic-low voltages for the en input are 1.4v and 0.4v, respectively. drive en high to turn on the device, and drive it low to place the device in shutdown. leaving en unconnected disables the device since the en is internally pulled low with a 0.5? current, however, a forced pulldown of en improves the noise immunity. the max5096/MAX5097 draw 6a (typ) of supply current when in shutdown. en with- stands up to +40v, allowing en to be connected direct- ly to in for always-on operation. the converter may be turned on and off while in both buck and ldo modes. each time the en is toggled, the output rises with a pro- grammed soft-start period. internal regulator (bp)/ undervoltage lockout the max5096/MAX5097 include an internal 4v auxiliary regulator to power internal circuitry. bypass the auxil- iary regulator output (bp) to sgnd with a 1f ceramic capacitor physically located close to the device. the regulator is not intended to supply the external circuit other than pulling up the ldo/ buck input or reset . do not load bp externally by more than 2ma. the regu- lator output is regulated to 4v with 7% accuracy during steady state. during turn-on, the bp voltage stabilizes after 250? with a 1? capacitor at bp. drive en high to turn on the internal regulator. the internal uvlo with hysteresis ensures stable operation, resulting in the monotonic rise of the output voltage. the uvlo circuit monitors the output of the regulator. the rising uvlo threshold is internally set to 3.65v (bp rising) with a 185mv hysteresis (bp falling). the 3.65v uvlo at the no-load bp output guarantees operation at v in lower than 4v. soft-start (ss) soft-start provides for the monotonic, glitch-free turn-on of the converter. soft-start limits the input inrush current which may cause a glitch, especially if the source impedance is high. the soft-start period required also depends on the output capacitance and the closed- loop bandwidth of converter. the soft-start period for the max5096/MAX5097 is externally programmable using a single capacitor (c ss ). the soft-start is achieved by the controlled ramping up of the error amplifier reference input. at startup, after v in is applied and the uvlo threshold is reached, the device enters soft-start. during soft-start, 5a is sourced into the capacitor (c ss ) connected from ss to sgnd (figure 2) causing the reference voltage to ramp up slowly. when v ss reaches 1.237v, the output becomes fully active. set the soft-start time (t ss ) using following equation: where v ss is 1.237v, i ss is 5?, t ss is in seconds, and c ss is in farads. pulling en low quickly discharges the c ss capacitor, making it ready for the next soft-start period. t v i c ss ss ss ss = max5096/MAX5097 40v, 600ma buck converters with low- quiescent-current linear regulator mode ______________________________________________________________________________________ 11
max5096/MAX5097 output voltage tracking/sequencing the output voltages of multiple max5096/MAX5097 converters can be made to track by using the ss pin during turn-on and turn-off (see figure 3). ss is pulled up using a 5? current source and connecting ss of multiple max5096/MAX5097s, raising the references with the same slope. tracking the converters reduces the differential voltages between the core and i/o volt- ages during turn-on, turn-off, and brownout. if any one converter output drops due to shutdown or an overload fault situation, the ss drops, pulling down all the con- verters simultaneously. the rate of fall of output volt- ages, however, depends on the output capacitance and load of the individual converter. multiple voltage sequencing can be done by daisy- chaining several max5096/MAX5097s. the reset of the first converter can be connected to en of the sec- ond converter. this allows the first converter to come up first every time the system is powered up. power-on reset output ( reset ) a supervisor circuit is integrated in the max5096/ MAX5097. reset is an open-drain output. reset pulls low as soon as v out drops below 90% of its nominal regulation voltage. once the output voltage rises above 92% of the set output voltage, the reset output enters a high-impedance state after the active timeout period (t rp ). the active timeout period is externally program- mable using a single capacitor from ct to ground. use the following equation to calculate the required timeout period for the power-on reset: where v ct-th is 1.237v, i ch is 1?, t rp is in seconds, and c ct is in farads. to obtain a logic-voltage output, connect a pullup resistor from reset to a logic-supply voltage. the internal open-drain mosfet can sink 1ma while provid- ing a ttl logic-low signal. if unused, ground reset or leave it unconnected. the power-on reset behavior is the same in both the ldo and buck modes of operation. oscillator/synchronization input (sync) the max5096/MAX5097 internal oscillator generates a factory-preset frequency of either 135khz (max5096) or 330khz (MAX5097). the 135khz version keeps the maximum fundamental frequency below 150khz, which keeps the third harmonic below 450khz and under the t v i c rp ct th ch ct = ? 40v, 600ma buck converters with low- quiescent-current linear regulator mode 12 ______________________________________________________________________________________ pgnd out lx v in gnd bp v in v out adj 22 h c out 22 f (cer.) comp sync d1* b260/ murs105 c in 100 f ldo/buck reset en ct ss c p 22pf c ss 0.047 f c ct 0.01 f 100k ? + 1.0 f max5096 MAX5097 r c 100k ? c c 1.2nf *use murs105 in applications where ldo mode quiescent current is critical. reset figure 2. fixed output voltage configuration
lower end of the am band. the max5096 is suitable for noise-sensitive applications like am radio power sup- ply. for an application where size is more important, use the MAX5097, which runs at 330khz frequency. the high-frequency operation reduces the size and cost of the external inductor and capacitor. the max5096/MAX5097 can be synchronized using an external signal. the max5096 can be synchronized from 120khz to 500khz, while the MAX5097 is capable of synchronizing from 300khz to 500khz. the external synchronization feature makes frequency hopping pos- sible depending on the selected am channel. connect sync to ground, if not used. thermal protection when the junction temperature exceeds t j = +165?, an internal thermal sensor signals the shutdown logic, which turns off the regulator (both in buck mode and ldo mode), and discharges the soft-start capacitor allowing the ic to cool. the thermal sensor turns the regulator on again after the ic? junction temperature cools by 20?, resulting in a cycled output during con- tinuous thermal-overload conditions. the thermal hys- teresis and a soft-start period limit the average power dissipation into the device during continuous fault con- dition. during operation, do not exceed the absolute maximum junction temperature rating of t j = +150?. applications information output voltage selection the max5096/MAX5097 can be configured as either a preset fixed output voltage or an adjustable output volt- age device. connect adj to ground to select the facto- ry-preset output voltage option (figure 2). the max5096a/MAX5097a and max5096b/MAX5097b provide a fixed output voltage equal to 3.3v and 5v, respectively (see the selector guide ). the max5096/ MAX5097 become an adjustable version as soon as the devices detect about 125mv at the adj pin. the resis- tor-divider at adj increases the adj voltage above 125mv and also adjusts the output voltage depending upon the resistor values. in adjustable mode, select an output between +1.273v and +11v using two external resistors connected as a voltage-divider to adj (figure 4). set the output voltage using the following equation: where v adj = 1.273v and r2 is chosen to be approxi- mately 100k ? . connect adj to gnd if adjustable mode is not used. inductor selection three key inductor parameters must be specified for proper operation with the max5096/MAX5097: induc- tance value (l), peak inductor current (i peak ), and inductor saturation current (i sat ). the minimum required inductance is a function of operating frequen- cy, input-to-output voltage differential, and the peak-to- peak inductor current ( ? i p-p ). higher ? i p-p allows for a lower inductor value, while a lower ? i p-p requires a higher inductor value. a lower inductor value minimizes size and cost and improves large-signal and transient response, but reduces efficiency due to higher peak currents and higher peak-to-peak output voltage ripple for the same output capacitor. on the other hand, high- er inductance increases efficiency by reducing the rip- ple current. resistive losses due to extra wire turns can exceed the benefit gained from lower ripple current lev- els, especially when the inductance is increased while keeping the dimension of the inductor constant. a good compromise is to choose ? i p-p equal to 40% of the full load current. calculate the inductor value using the fol- lowing equation: l vvv vf i out in out in sw p p = ? ? () ? vv r r out adj =+ ? ? ? ? ? ? 1 1 2 max5096/MAX5097 40v, 600ma buck converters with low- quiescent-current linear regulator mode ______________________________________________________________________________________ 13 v out3 v out2 v out1 soft-start stop ratiometric tracking outputs sequenced outputs stop soft-start v out3 v out2 v out1 figure 3. output voltage tracking/sequencing
max5096/MAX5097 use typical values of v in and f sw so that efficiency is opti- mum for typical conditions. the switching frequency (f sw ) is fixed at 135khz (max5096) and 330khz (MAX5097). f sw can also be varied from 120khz to 500khz (max5096) and from 300khz to 500khz (MAX5097) when synchronized to an external clock (see the oscillator/ synchronization input (sync) section). the peak-to-peak inductor current, which reflects the peak-to-peak output ripple, is worst at the maximum input voltage. see the output capacitor selection section to verify that the worst-case output ripple is acceptable. the inductor satu- rating current (i sat ) is also important to avoid runaway current during continuous output short circuit. select an inductor with an i sat specification higher than the maxi- mum peak current limit of 1.9a. the buck mode operation determines the inductor and output capacitor values. however, the values of the inductor, its dcr, and the output capacitance/esr affect the closed-loop transfer function both in buck and ldo modes. the internal compensation of the max5096/MAX5097 in ldo mode limits the values of these external components. make sure that the combi- nation of output inductor, capacitor, and esr falls with- in the range specified in following table 1. output capacitor selection the allowable output voltage ripple and the maximum deviation of the output voltage during load steps deter- mine the output capacitance and its esr. the output 40v, 600ma buck converters with low- quiescent-current linear regulator mode 14 ______________________________________________________________________________________ pgnd out lx v in gnd bp 5v to 40v v in v out adj 22 h c out 22 f comp sync d1* b260/ murs105 c in 100 f ldo/buck reset en r c c c ct ss c p r pu + 1.0 f max5096 MAX5097 r1 r2 c ct c ss reset *use murs105 in applications where ldo mode quiescent current is critical. figure 4. adjustable output voltage configuration inductor output capacitor (c out ) 22?, esr = 5m ? to 20m ? (ceramic) 47?, esr = 40m ? to 150m ? 100?, esr = 30m ? to 100m ? 22? 470? / esr = 60 ? to 400m ? 22?, esr = 5m ? to 20m ? (ceramic) 47? / esr = 40m ? to 150m ? 100? / esr = 30m ? to 100m ? 47? 470? / esr = 60m ? to 400m ? 22?, esr = 5m ? to 20m ? (ceramic) 47? / esr = 40m ? to 150m ? 100? / esr = 30m ? to 100m ? 100? 470? / esr = 60m ? to 400m ? table 1. inductor/output capacitor selection
ripple is mainly composed of ? v q (caused by the capacitor discharge) and ? v esr (caused by the volt- age drop across the esr of the output capacitor). normally, a good approximation of the output voltage ripple is ? v ripple ? v esr + ? v q . if using ceramic capacitors, assume the contribution to the output volt- age ripple from the esr and the capacitor discharge to be equal to 20% and 80%, respectively. if using alu- minum electrolyte capacitors, assume the contribution to the output voltage ripple from the esr and the capacitor discharge to be equal to 90% and 10%, respectively. use the following equations for calculating the output capacitance and its esr for required peak-to-peak out- put voltage ripple. ? i p-p is the peak-to-peak inductor current and f sw is the converter? switching frequency. the allowable deviation of the output voltage during fast load transients also determines the output capaci- tance, its esr, and its equivalent series inductance (esl). the output capacitor supplies the load current during a load step until the controller responds with a greater duty cycle. the response time (t response ) depends on the closed-loop bandwidth of the converter (see the compensation network section). the resistive drop across the output capacitor? esr, the drop across the capacitor? esl, and the capacitor dis- charge, causes a voltage drop during the load step. use a combination of low-esr tantalum/aluminum elec- trolytic and ceramic capacitors for better transient load and voltage ripple performance. non-leaded capaci- tors and/or multiple parallel capacitors help reduce the esl. keep the maximum output voltage deviation below the tolerable limits of the electronics being pow- ered. use the following equations to calculate the required esr, esl, and capacitance value during a load step: where i step is the load step, t step is the rise time of the load step, and t response is the response time of the controller. the response time of the converter is approximately one third of the inverse of its closed-loop bandwidth and also depends on the phase margin. rectifier selection the max5096/MAX5097 require an external schottky/ fast-recovery diode rectifier as a freewheeling diode. connect this rectifier close to the device using short leads and short pc board traces. choose a rectifier with a continuous current rating greater than the high- est output current-limit threshold (1.9a) and with a volt- age rating greater than the maximum expected input voltage, v in . use a low forward-voltage-drop schottky rectifier to limit the negative voltage at lx. avoid higher than necessary reverse-voltage schottky rectifiers that have higher forward-voltage drops. use a 60v (max) schottky rectifier with a 2a current rating. the schottky rectifier leakage current at high temperature significant- ly increases the quiescent current in ldo mode. in applications where ldo mode quiescent current is important, use an ultra-fast switching diode to limit the leakage current. in this type of application, use murs105, murs120 for their fast-switching and low- leakage features. input capacitor selection the discontinuous input current of the buck converter causes large input ripple currents and therefore, the input capacitor must be carefully chosen to keep the input voltage ripple within design requirements. the input voltage ripple is comprised of ? v q (caused by the capacitor discharge) and ? v esr (caused by the esr of the input capacitor). the total voltage ripple is the sum of ? v q and ? v esr . calculate the input capaci- tance and esr required for a specified ripple using the following equations (continuous mode): i out_max is the maximum output current and d is the duty cycle. esr v i i c idd vf where i vv v vf l and d v v esr out max pp in out max qsw pp in out out in sw out in = + ? ? ? ? ? ? = ? = ? = ? ? ? ? ? ? _ _ () () 2 1 esr v i c it v esl vt i esr step out step response q esl step step = = = ? ? ? ? c i vf esr v i out pp qsw esr pp = = ? ? ? ? ? ? 16 max5096/MAX5097 40v, 600ma buck converters with low- quiescent-current linear regulator mode ______________________________________________________________________________________ 15
max5096/MAX5097 compensation network the max5096/MAX5097 in ldo mode are compensat- ed internally with a compensation network around the ldo error amplifier. when in buck mode, the dc-dc g m amplifier must be externally compensated using a network connected from comp to ground. the current- mode control architecture reduces the compensation network to a single pole-zero. the rc and c network, connected from the internal transconductance amplifier output to sgnd, can provide a single pole-zero pair. choose all the power components like the inductor, output capacitor, and esr first and design the com- pensation network around them. choose the closed- loop bandwidth (f c ) to be approximately 1/10 of the switching frequency. see the following equations to cal- culate the compensation values for the low-esr output capacitor with esr zero frequency, approximately a decade higher than f c . calculate the dominant pole due to the output capaci- tor (c out ) and the load (r out ): where r out = v out / i load . calculate the r c using following equation: where g mc is the control to output gain of the max5096/MAX5097 buck converter and is equal to 1.06. v adj is the feedback set point equal to 1.237v and g m (transconductance amplifier gain) is equal to 136?. see figure 2. place a zero (f z ) at 0.9 x f po : finally, place a high-frequency pole at the frequency equal to half of the converter switching frequency (f sw ). place the compensation network physically close to the max5096/MAX5097. switching between ldo mode and buck mode the max5096/MAX5097 switch between the buck mode and ldo mode on the fly. however, care must be taken to reduce output glitch or overshoot during the switching. buck mode to ldo mode the ldo mode is intended for the low 100ma output current while the buck converter delivers up to 600ma output current. it is important to first reduce the output load below 100ma before switching to the ldo mode. if the output load is higher than 100ma, the max5096/MAX5097 may go into the current limit and the output will drop significantly. whenever the mode is changed, output is expected to glitch because the loop dynamics change due to different error amplifiers when operating in the ldo and buck modes. the output volt- age undershoot can be minimized by reducing the out- put load during switching and using larger output capacitance. ldo mode to buck mode when switching from the ldo mode to buck mode, a fixed amount of delay (32 cycles) is applied so that the buck converter control loop and oscillator reach their steady-state conditions. the 32-cycle delay translates to approximately 250? and 100? for 150khz and 330khz switching frequency versions, respectively. it is recommended that the output load of 600ma must be delayed by at least this much time to allow the max5096/MAX5097 to switch to high-current buck mode. this ensures that the output does not drop due to the ldo current-limit protection mechanism. pc board layout guidelines 1) proper pc board layout is essential. minimize ground noise by connecting the anode of the free- wheeling rectifier, the input bypass capacitor ground lead, and the output filter capacitor ground lead to a large pgnd plane. 2) minimize lead lengths to reduce stray capacitance, trace resistance, and radiated noise. in particular, place the schottky/fast recovery rectifier diode right next to the device. c rf p csw = 1 c rf c cfpo po = 1 2 r vf gr gv f c oc mc out m adj po = f cr po out out = 1 2 40v, 600ma buck converters with low- quiescent-current linear regulator mode 16 ______________________________________________________________________________________
max5096/MAX5097 40v, 600ma buck converters with low- quiescent-current linear regulator mode ______________________________________________________________________________________ 17 part output voltage (v) switching frequency (khz) max5096a_ _ _ +3.3/adjustable 135 max5096b_ _ _ +5.0/adjustable 135 MAX5097a_ _ _ +3.3/adjustable 330 MAX5097b_ _ _ +5.0/adjustable 330 selector guide chip information process: bicmos 3) connect the exposed pad of the ic to the sgnd plane. do not make a direct connection between the exposed pad plane and sgnd (pin 2) under the ic. connect the exposed pad and pin 2 to the sgnd plane separately. connect the ground connection of the feedback resistive divider, the soft-start capaci- tor, the adjustable reset timeout capacitor, and the compensation network to the sgnd plane. connect the sgnd plane and pgnd plane at one point near the input bypass capacitor at v in . 4) use the large sgnd plane as a heatsink for the max5096/MAX5097. use large pgnd and lx planes as heatsinks for the rectifier diode and the inductor.
max5096/MAX5097 40v, 600ma buck converters with low- quiescent-current linear regulator mode 18 ______________________________________________________________________________________ package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) qfn thin.eps
max5096/MAX5097 40v, 600ma buck converters with low- quiescent-current linear regulator mode ______________________________________________________________________________________ 19 package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)
max5096/MAX5097 40v, 600ma buck converters with low- quiescent-current linear regulator mode maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 20 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2006 maxim integrated products is a registered trademark of maxim integrated products, inc. boblet tssop 4.4mm body.eps e 1 1 21-0108 package outline, tssop, 4.40 mm body, exposed pad xx xx package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)

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